AI chip test push puts Teradyne UltraFLEXplus in the spotlight

Edited by ad hoc news Flagship & Bestseller Desk. Reviewed before publication on 06/15/2026 at 7:45 PM ET. Details in the imprint.

UltraFLEXplus, Teradyne’s current high-performance automated test platform for complex system-on-chip devices, is drawing fresh attention as chipmakers race to qualify ever larger AI and data center processors. The system, positioned as the company’s flagship digital and mixed-signal test platform, targets advanced logic devices built at 5 nm and below and is now being paired with Tokyo Electron’s latest wafer probers for production AI chiplet test. According to Teradyne’s product documentation, UltraFLEXplus builds on the long-running UltraFLEX family with higher pin counts, faster digital speeds and expanded instrumentation tailored to multi-die, high-bandwidth memory and chiplet-based packages. Teradyne’s official product page describes it as the company’s most capable SOC test cell for advanced nodes.

What UltraFLEXplus is designed to test

At its core, UltraFLEXplus is a modular automatic test equipment (ATE) platform aimed at high-volume production testing of complex SOCs used in smartphones, networking gear, automotive controllers and, increasingly, AI accelerators and data center processors. Teradyne specifies that the system supports high-speed digital channels with edge rates suited to multi-gigabit interfaces, along with analog, RF and power options that can be configured depending on the device under test. The architecture allows customers to scale from a few hundred pins to more than a thousand pins within a single test cell, enabling parallel test of large packages to improve throughput at wafer sort and final test. The company’s marketing material also emphasizes software compatibility with existing UltraFLEX test programs, which helps large chipmakers migrate to UltraFLEXplus without re-writing entire test suites and reduces time to production.

A key requirement for modern AI and high-performance computing devices is the ability to test chiplets and stacked configurations, including combinations of compute dies and high-bandwidth memory. UltraFLEXplus addresses this by supporting advanced thermal control, power delivery and signal integrity features that maintain stability as devices draw high currents and switch at extreme speeds. Teradyne highlights options for advanced instrumentation to handle fast SerDes links and large memory arrays, which are central to GPU-class and custom accelerator designs. Industry reports on Teradyne’s portfolio note that UltraFLEXplus sits at the high end of the company’s semiconductor test segment, above its mid-range SOC testers, and is one of the main platforms expected to benefit from the ongoing AI and data center investment cycle. One recent market commentary on Teradyne pointed out that the company’s automatic test equipment portfolio, including UltraFLEXplus, is tightly linked to customer roadmaps in advanced logic and memory manufacturing. A MarketBeat analysis of Teradyne’s business underlined that semiconductor test remains a core earnings driver.

This focus on advanced SOC and AI devices received an additional boost from a new collaboration with Japan’s Tokyo Electron, one of the world’s major wafer fab equipment makers. Earlier this month, the two companies announced a jointly developed, production-ready integrated test cell that combines UltraFLEXplus with Tokyo Electron’s Prexa SDP prober to improve known-good-die screening for advanced AI and data center chiplet packages. The combined solution is designed to perform electrically comprehensive tests at wafer level, helping customers identify defective chiplets before assembly, which is critical when a single finished module can contain dozens of expensive dies. According to coverage of the partnership, the integrated cell aims to shorten time to ramp for new AI devices and to lower the overall cost of test by increasing parallelism and reducing handling steps. A Simply Wall St report on the Tokyo Electron tie-up highlighted UltraFLEXplus as the central test platform in this AI-focused cell.

Within Teradyne’s broader lineup, UltraFLEXplus sits alongside other semiconductor test platforms such as the ETS series for power and automotive devices and the J750 family for consumer and microcontroller applications, but it is the UltraFLEX lineage that typically addresses the most advanced logic nodes. The company has signaled in presentations that demand for high-end SOC testers tends to track new technology nodes at major foundries and integrated device manufacturers, meaning that capital spending cycles at leading-edge customers can heavily influence UltraFLEXplus shipments. While unit pricing for such complex ATE systems is not generally disclosed in public materials, industry estimates place the cost of a fully configured high-end SOC tester, including handlers and probers, in the multi-million-dollar range, reflecting both the hardware complexity and the specialized software that underpins test development and data analysis.

For Teradyne, UltraFLEXplus is strategically important because it anchors the company’s position in AI, 5G and high-performance computing test, areas where customers require both raw performance and a long roadmap for future enhancements. Management has recently emphasized AI-related opportunities when discussing the company’s prospects, and UltraFLEXplus is one of the main platforms through which those opportunities are realized at the factory floor. Shares of Teradyne (ISIN US8807701029) trade on the Nasdaq under the ticker TER; according to recent market data, the stock has been buoyed in part by expectations that demand for advanced test platforms like UltraFLEXplus will remain strong as AI and data center chips grow in complexity.

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