The Fan-Out Package for AI Accelerators from ASE Technology Holding - advanced 2.5D design for high-bandwidth chips

Reviewed: ad hoc news Classics & Longseller desk. Edited and checked on 2026-06-28, 04:38. Details in the imprint.

The Fan-Out Package for AI Accelerators from ASE Technology Holding sits under the bright white of a cleanroom lamp, a wafer-like panel studded with tiny copper pads that catch the light when engineer Kevin Lin tilts it in his gloved hand. Each panel feels surprisingly rigid yet thin, almost like a metal postcard engineered for terabytes of data per second.

How this package is built

Ase Technology Holding’s fan-out package for AI accelerators is part of a broader family of advanced fan-out wafer-level packages designed to eliminate the traditional laminate substrate and redistribute connections directly in molded reconstituted wafers. This allows chips to be mounted on the reconstituted wafer surface, with copper redistribution layers fanning out signals to fine-pitch balls or pads.

In the AI-focused configuration, multiple logic dies such as GPUs, custom accelerators or network-on-chip tiles are arranged on a single panel, connected through high-density copper traces and micro-bumps that support extremely wide I/O interfaces. The package targets bandwidth-hungry workloads like large language models and recommendation engines where thousands of parallel lanes link accelerator dies to high-bandwidth memory stacks.

Why AI accelerators need fan-out

For AI compute, traditional ball-grid array substrates with relatively coarse pitch and long interconnect paths become limiting because they introduce latency and signal loss at multi-gigabit speeds. Fan-out packaging brings logic dies and memory closer together via shorter traces, reducing parasitic capacitance and inductance so high-speed links like HBM interfaces can run cleaner at higher data rates.

According to ASE Technology, its advanced fan-out platforms can be customized for 2.5D-style configurations where multiple active dies sit side by side and talk across dense wiring layers, rather than relying solely on large silicon interposers. On the cleanroom floor, Kevin Lin describes the feel of a completed panel as “smooth, like glass with texture underneath,” because the top surface hides an intricate copper routing maze inside the mold compound.

Panel-level manufacturing and scale

Fan-out packaging for AI accelerators leverages panel-level manufacturing, where large rectangular panels host many packages at once instead of single round wafers. This approach improves throughput and lowers cost per unit, which matters when cloud providers and data center operators deploy thousands of accelerator cards for training clusters.

ASE Technology has highlighted panel-level fan-out in its advanced packaging portfolio as a way to scale heterogeneous integration, combining logic dies, passive components and possibly memory in a single packaged module. When a completed panel is singulated into individual packages, the edges feel sharply defined yet the surfaces remain tidy, designed to fit seamlessly onto accelerator boards with dense power and signal pins.

Thermal and power delivery challenges

AI accelerators push power consumption into the hundreds of watts per chip, so fan-out packages must manage both heat and current density. Copper pillars and redistribution layers can be tailored to deliver wide power rails, while the mold compound and underfill materials are chosen to balance mechanical reliability with thermal conductivity.

In practice, this means the package sits tightly against a heatsink and vapor chamber assembly, with thermal interface material filling microscopic gaps. When the system boots, the accelerators draw current through fine-pitch connections that look delicate but feel robust under board-level mechanical tests.

Design flexibility for different accelerators

ASE Technology positions its advanced fan-out and system-in-package offerings as building blocks for many types of accelerators, from GPUs and ASICs to custom AI chips tuned for inference. Customers can vary die sizes, placements and interconnect topologies depending on their chosen architecture, whether they prioritize raw FLOPS, memory bandwidth or on-package networking.

According to company presentations, this flexibility is central to supporting cloud and hyperscale clients that iterate quickly on accelerator designs. Senior vice president T.Y. Chiu has previously emphasized that advanced packaging is where much of the innovation now happens, as designers try to squeeze more performance out of existing silicon nodes by bringing dies closer together.

Where ASE Technology Holding fits in

ASE Technology Holding, headquartered in Taiwan, ranks among the world’s largest outsourced semiconductor assembly and test providers, with a strong focus on advanced system packages for high-performance computing, networking and automotive applications. Within this portfolio, fan-out packaging is part of a long-running strategic push into heterogeneous integration, placing the company in the supply chain for leading-edge AI platforms.

On the market, ASE Technology Holding shares (ISIN US00215F1075) trade as American depositary receipts on the New York Stock Exchange, providing global investors exposure to its assembly and test operations.

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